1. Field of the Invention
The present invention relates to testing apparatus and methods, and, more particularly, to an apparatus and method for testing stacked integrated circuit (IC) packaging structures.
2. Description of Related Art
3D IC chip stacking packaging technologies have been developed for integrating more electronic elements and functions in a limited area to meet the requirements of multi-function and miniaturization as demanded by electronic products.
3D IC chip stacking packaging technologies involve stacking and integrating a plurality of chips having different functions, characteristics or substrates through through-silicon via (TSV) technology, which is also referred to as 2.5D IC technology, on the other hand, the current 3D IC technologies individually make these different functional chips by the most appropriate fabrication processes and then integrate the chips with TSVs, to thereby shorten signal transmission distance and reduce conductive resistance and chip size. Therefore, the advantages of package scaling, high integration, high efficiency, low power consumption, and low cost can be realized to meet the miniaturization requirement of digital electronics.
To test a 3D IC (or 2.5D IC) chip structure, especially semiconductor elements having TSVs, is critical for mass production. Testing a semiconductor element generally includes a chip probe (CP) test before a packaging process and a final test (FT) after the packaging process.
FIGS. 1A and 1B illustrate a chip probe test performed on an element 7. The element 7 to be tested is a wafer substrate 9 having TSVs 90 formed therein and chips 8 bonded thereon. The element 7 is disposed on a testing apparatus 1. The testing apparatus 1 has a base 10 and a lid 11. The element 7 contacts both the base 10 and the lid 11 through compression pressure such that pogo pins 110 of the lid 11 are in electrical connection with electrical contacts 91 on an upper side of the wafer substrate 9 to form an electrical circuit loop L1, and electrical circuits 100 and conductive bumps 101 of the base 10 are in electrical connection with electrical contacts 92 on a lower side of the wafer substrate 9 to form an electrical circuit loop L2, thereby enabling a double-side (upper and lower sides) probe test.
However, since a wafer substrate 9 with TSVs is 10 μm to 180 μm thick only, the wafer substrate 9 is easy to crack when the pogo pins 110 come into contact with the wafer substrate 9 downwards. The contact pressure in fact easily do damage to the wafer substrate 9.
Furthermore, the double-side electrical circuit loops L1, L2 complicate the electrical circuit layout. The structure only enables to perform a CP test before the packaging process and does not do an FT test after the packaging process. Therefore, the present technology cannot have a testing apparatus that provides both CP and FT tests for an element having TSVs to be tested.
In addition, the contact pressure can cause inaccurate alignment in the electrical circuit loops L1, L2.
Therefore, it is dispensable that there is a need to invent a testing apparatus and method to overcome the above-described disadvantage.